Technical Summary

Table of Contents
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Introduction
A disproportionate share of vendor investment and customer attention have been applied to the late stages of Field Programmable Gate Array (FPGA), Application-Specific IC (ASIC) and Custom IC design, where designs are finally verified and adjustments made to programs so that hardware can be made to work correctly in its intended application. With the introduction of CoverMeter, a relatively small investment toward the front end of the design process can yield far fewer problems at the back end, resulting in higher reliability and shortened design-to-deployment cycles with fewer resources expended over a shorter period of time.

 CoverMeter is a revolutionary coverage tool measured both by its comprehensive suite of tests and reporting options and its efficiency in operation. Working with both behavioral and structural Verilog HDL designs, CoverMeter provides definitive test coverage and debugging information throughout the design cycle, pinpointing specific portions of your logic which are unexercised, duplicated, or illegal. And the user need not wait until the last step before the design release to perform coverage analysis.

 CoverMeter tracks the following categories of coverage information:

 Source Code coverage

• Statements
• Blocks
• Branches

 Condition coverage

• Conditional paths
• Logical Operators
• Parenthesized expressions
• Variables
• Assign Statement conditions
• Event conditions

 User-Specified-Expression coverage

• State machines - states and transitions
• Data transfers - register transfer and busses
• Invariant and association - illegal states and conditions

 Toggle coverage

• Registers and nets
• Average toggle per cycle

CoverMeter is now available for a variety of platforms from Advanced Technology Center. This product was under development for more than three years and its broad functionality is the result of an ongoing collaboration between CoverMeter’s developers and its key early adopters, design teams within some of the foremost companies in the fields of high-performance workstations, instruments and communications networks. Each of these customers contributed considerably to the extent of testing supported in this product. Not until these customers and its designers were completely satisfied was CoverMeter was the product launched as a commercial offering in September, 1996. A summary of this product’s exceptional capabilities follows in the succeeding pages.

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 Source Code Coverage - Statements, Blocks and Branches

CoverMeter monitors source code execution as the simulation progresses, keeping track of every module and its instances. You can select module instances, hierarchies and specific lines for monitoring.

To obtain accurate and meaningful coverage information, CoverMeter breaks physical lines into statement, groups of statements into blocks and eliminates purely structural elements from consideration. It goes a step further by identifying and providing coverage for implied conditional statements such as ELSE when the IF-THEN-ELSE does not explicitly specify the ELSE statement in the source code.

CoverMeter probes at appropriate locations in the source code to make the monitoring process fast and efficient. The source code monitoring targets the following source code features:

CoverMeter generates a set of reports which provide easy access to coverage information of all these features. Reports also include source code annotated with coverage information. Using these annotated reports, the users can directly examine the impact of coverage results on the design verification effort. The reports separate detailed, concise and summary information into different files. For example, you can examine each individual statement or only those statements that were not executed. Coverage summaries are produced to identify instance-by-instance and hierarchy-by-hierarchy statistics.

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Condition Coverage - Conditional Paths
CoverMeter provides advanced features for condition coverage allowing you to conduct in-depth and thorough analysis of all the paths in your design. Conditions are automatically extracted from the conditional statements of the source code.

One of the truly distinctive features of CoverMeter is the extent of control and flexibility provided to the designer in directing how the various features are used. We understand that not all conditions in the expressions translate to the paths in the design. Some conditions may be irrelevant for the design coverage consideration or perhaps not useful at a particular stage in the design verification process. That is why the features are devised in a way that allow the designer to zoom in on the conditions of his/her interest. This prevents the designer from having to examine mounds of information that are either inapplicable or extraneous to the analysis being conducted.

Conditions extracted from any statement can be monitored for coverage as each individual condition, or can be monitored along with other related conditions for simultaneous coverage.

Conditions considered for coverage include:

  • Sub-expressions connected through logical operators
  • Sub-expressions specified in parentheses
  • Variables in expressions
  • Events expressed in ALWAYS statements
  • Expressions from conditional ASSIGN statements

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Condition Coverage - Logical Operators
When a conditional expression contains sub-expressions connected by a logical operator such as && or ||, CoverMeter extracts these sub-expressions and presents each of these to the designer for specific monitoring. Conditional expressions are part of a conditional statement such as IF and WHILE statements. These sub-expressions translate to actual logical paths in the synthesized design. When a test exercises a function in the design, the coverage of these sub-expressions clearly indicate whether a hardware path is being traversed.

The following example illustrates this feature:

If (((a==2) && (!b)) || (c & d))
begin
...
...
end

The following conditions are monitored either stand-alone or simultaneously:

(a= =2)
(!b)
((a= =2) && (!b))
(c & d)
For && operator
For && operator
For || operator
For || operator

The stand-alone coverage of conditions is shown below, where 1 indicates that the condition was true some time during the simulation, while 0 indicates that the condition was false some time during the simulation. The absence of 0 signifies that the condition was never false. Similarly, the absence of 1 indicates that the condition was never true. 

CONDITION



CONDITION



CONDITION


CONDITION
(a==2)
0
1

(!b)
0
1

((a==2)&&(!b))
1

(c & d)
0

The following case illustrates the simultaneous coverage of conditions. Here, the simultaneous occurrence of conditional values is indicated.

CONDITION


CONDITION
(a==2)
0
0
((a==2) && (!b))
0
1
(!b)
1
0
(c & d)
1
1

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Condition Coverage - Parenthesized Expressions
While logical operators can indicate many important paths in the design, there are cases when some other sub-expressions translate to critical paths. CoverMeter provides an option which makes possible the monitoring of any parenthesized expression of a conditional statement. An expression that is enclosed in parenthesis becomes a candidate for coverage. The user can selectively activate a module for parenthesized expression coverage, and prevent impertinent information from being included in the reported results.

An example below illustrates this feature:

If (((a==2) & (!b)) == (c>>1))
begin
...
...
end

The following conditions are monitored:

(a==2)
(!b)
((a==2) & (!b))
(c>>1)

As with the other tests cited earlier, these conditions can be monitored stand-alone or simultaneously. If a condition is never true or never false, it indicates either that a certain path was not exercised or that the path is not useful for executing the function. In either case, CoverMeter provides the designer with guidance to take the appropriate action.

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Condition Coverage - Variables
Another special case for a detailed coverage analysis often arises when the sub-expression coverage information is not sufficient to determine whether a path is traversed. The knowledge of specific values for a variable encountered during testing becomes essential to resolving the ambiguity of paths. Again, CoverMeter caters to these special needs and furnishes options to satisfy the coverage information when the situation arises.

The insight obtained by the values of variables can be used in variety of ways: one of many possible paths covered, broad range of simulated values, buss traffic, variety of test cases, etc. All of these strengthen the confidence in the breadth of testing and clearly point out the level of further effort required to complete the design verification process. The user can selectively activate any module for variable coverage and restrict the explosion of coverage information.

An example below illustrates this feature:

If (((a==2) & (!c)) || (e == (d>>1)))
begin
...
...
end

The following variables are monitored for their values, for either stand-alone or simultaneous coverage:

a
b
c
d
e

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Condition Coverage - ASSIGN Expression
One of the most frequently used statements to describe logic is the ASSIGN statement. When an ASSIGN statement specifies a condition, it translates into distinct logical paths of interest to the designer. The coverage results of the condition associated with the ASSIGN statement indicate which logical paths were exercised.

An ASSIGN statement is always executed in contrast to other behavioral statements. CoverMeter monitors these paths in an appropriate event-driven fashion, optimizing the execution speed and providing results in an easy-to-understand format. Like other features, the monitoring can be selective on the choice of modules and hierarchies.

An example below illustrates this feature:

1 assign g = (in>5) ? 1 : 0;
2 assign h = ((a & b) ^ c) ? (e>>1) : (f>>1);
...
...
...

The following conditions are monitored:

(in>5) For ASSIGN statement on line 1
((a&b) ^ c) For ASSIGN statement on line 2

The above ASSIGN statements translate to a simple multiplexing operation. The coverage is provided for the select signal and the corresponding path of the multiplexor.

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 Condition Coverage - EVENT Conditions
Another powerful feature of CoverMeter is the capability to monitor events taking place in the simulator. The Verilog language uses an event-driven paradigm for simulation of signals. The event-driven mechanism is expressed by the ALWAYS statement. The execution of an ALWAYS statement block is conditioned on the arrival of events which are explicitly specified as part of the ALWAYS statement.

The coverage of events records activities that trigger assignment of registers or other variables in the design. The absence of a specific event points to problems in the design or test bench. Sometimes this coverage information is useful for debugging purposes.

CoverMeter tracks events on an optional basis. When required, it produces coverage of events marking simulation activities when they occur and indicating the absence of these events in other cases.

An example below illustrates this feature:

Always @ ((a & b) or (d==e))
begin
...
...
...
end

The following events are monitored:

(a & b) For first event
(d==e) For second event

The events can be monitored for stand-alone or simultaneous coverage. The intuitive style of the results for conditions is also maintained for event coverage.

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 User-Specified Expression Coverage

CoverMeter offers a unique feature of user-specified expressions. This feature opens up the avenues for not only insightful coverage information, but also presents you with extraordinary debugging aids not available with even the most powerful front-end tools.

With this powerful testing aid, you can obtain the most complex and hidden aspects of your system implementation during an on-going simulation. You can judiciously choose to focus on what is of interest to you, rather than to obtain irrelevant or false information generated from source code statements.

Here are some of the useful applications of these features:

This powerful feature of expressions customized for any specific use is over and above the automatic condition coverage provided by other features.

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State Machine Coverage - States and Transitions
Designers often detect functional errors in their ASIC or FPGA design due to incomplete testing of state machines, one of the most difficult design verification tasks. Testing becomes even more difficult when interactions between states of two different state machines are critical to the performance of the design.

CoverMeter provides you with an intuitive syntax to specify your state machines. Once specified, CoverMeter will pinpoint coverage for what you want to see in the reports to help the designer make the task of coverage analysis both efficient and controlled. You don’t need to spend hours in dissecting meaningful information from false information. The coverage for your state machine includes:

Using these features, you can specify complex interactions between multiple state machines and their transitions. The interactions can be specified as equations in familiar Verilog syntax, supported by Verilog INCLUDE and DEFINE statements. To cut down on the specification effort of listing expected coverage data, CoverMeter allows handy notation such as the wild card(*) for any value, don’t care values (X), transition (->) and numbers in any commonly used radix.

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 Data Transfer Coverage - Register Transfer and Busses
CoverMeter assists you in what can be the daunting task of deciphering the kind of data transfer activities taking place on busses and between the registers. Data transfers and data mapping are primary functions of products used by many industries such as telecommunication and networking. CoverMeter can monitor data busses, vectored data variables or data mapping equations that can represent abstract or actual data activities. Coverage analysis can take place at a much higher level of description when the product is being conceptualized, and later can be used to decide on the implementation of the design.

CoverMeter can replace guess-timation with real numbers that represent the actual data being simulated. You can use these numbers to determine if there has been a sufficient amount of data transfer activities and variation of data has been simulated in different portions of the design.

Complex data mapping algorithms require special attention to the boundary conditions and corner cases which can cause systems to fail in unpredictable circumstances. CoverMeter validates the testing of these peculiar and potentially risky situations.

CoverMeter can keep track of a range of values for

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Invariant Coverage - Illegal States and Conditions
Unlike other tools, CoverMeter has a special feature to address the determination of correct and incorrect behavior of systems. A good verification plan implements tests not only for correct behavior of the system, but also for possible modes of failure and unpredictable situations. The knowledge that none of the system invariants and conditions have been violated is a confidence-builder that cannot be obtained from other coverage information.

Relying upon this feature, you can conveniently detect any system state or condition that is considered illegal or undesirable. More importantly, CoverMeter will identify all failing conditions related to a system invariant or a true condition. A system state can be any complex relationship between state variables, registers or nets.

How one goes about applying this feature is very simple.

All CoverMeter features work in regression mode. The results are accumulated from one test to another.

The objective of all this analysis is very simple: to produce products that are bug-free and behave in a predictable fashion. CoverMeter, equipped with these powerful features, offers you the opportunity to fulfill this objective, and meet your product development challenges with confidence.

From the information presented at the end of your regression suite, you will be well on your way to dramatically improving the quality of your design in a timely manner.

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 Toggle Coverage - Toggle Activity and Power Consumption Estimation

CoverMeter offers you an opportunity to be an additional step ahead in your design process. Integrated into CoverMeter is a well-known toggle coverage technique that has long been regarded important by hardware designers as the most fundamental coverage analysis. You will not need to wait until the gate-level fault analysis and fault simulation is performed just to ensure that all elements of the system have been exercised.

CoverMeter monitors each net and register for any value transition from 0->1 and 1->0. Toggle Monitoring is made so flexible that you can

Toggle coverage can be obtained on behavioral and structural designs. The results definitely point out inactive elements and unexercised portions of the design by indicating missing transitions of values. Module by module statistics can be quickly examined to determine low coverage portions. The average toggle per clock cycle is used to estimate power requirements. CoverMeter keeps track of switching on elements every clock cycle and calculates average as the simulation progresses. Although power dissipation can not be precisely calculated in this manner, the average toggle per cycle has been widely used as an indispensable early-on predictor in the pre-layout phase to indicate any problems later on.

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Summary
CoverMeter offers facilities for thorough testing of Source Code, Conditions, User-Specified Expressions and Toggles, making this product the most comprehensive code coverage tool available today from any source. Reports are user-configurable, allowing users to not only thoroughly evaluate their designs for coverage, but also to share these coverage test results in an understandable fashion with management and others of their technical teams. CoverMeter is available for all popular platforms, including Sun SPARC, Hewlett Packard, DEC Alpha and Windows NT platforms. And CoverMeter works with all Verilog simulators that support the PLI interface standard, including simulators from industry leaders Cadence, Viewlogic and Frontline.

Evaluation packages are available for qualified customers. Click Here to request an evaluation of CoverMeter in your development environment. We also invite you to call Advanced Technology Center (ATC) at (714) 583-9119 to discuss your code coverage needs with an Account Manager.