|Are We Done Yet?
This is the question so often posed by managers and designers who are anxious to move their system from the design phase to fabrication and prototype testing phase. No one wants to release an unexercised and untested system for fabrication. The consequences are all too familiar: system functional errors, cost overruns and product introduction delays.
CoverMeter is used by designers of FPGA, ASIC and Custom IC-based systems to determine just how much design verification is required to produce error free designs in the very first fabrication run. With the complexity and size of systems growing by leaps and bounds, every designer needs a powerful aid to manage the quality and cost of future products. CoverMeter is a pioneering functional coverage tool with the breadth of coverage to ease these concerns. While you perform your behavioral or structural system testing in Verilog, CoverMeter works behind the scenes to monitor source code, element activities and user expressions. The result of all this background work is provided as coverage information and metrics that include a wide range of observations from conditional sub-expressions to statements to toggle activity.
CoverMeter works on behavioral as well as structural Verilog HDL designs. CoverMeter provides definitive test coverage and debugging information throughout the design cycle to track progress so that you need not wait until the last step before the design release to perform coverage analysis. CoverMeter pinpoints specific portions of your logic which are unexercised, duplicated, or even illegal.
Is The Key
CoverMeter is flexible and user-controllable in all aspects of its features, allowing you to select from as high granularity as design hierarchies to as fine as specific bits of a vector net or specific lines of code. You can select design hierarchies, modules, source code, conditions and elements (nets and registers) for coverage. And in doing so, you can focus on problematic portions of your design, rather than sifting through pages of superfluous coverage information. CoverMeter not only saves you time, but produces coverage results that can directly be used as a pass/fail criteria for releasing a design to fabrication.
CoverMeter is ideal for regression testing where the simulations are performed over distributed computing resources. You can transfer results from one simulation run to the next in a flexible manner that eliminates the need for hours of post processing.
CoverMeter generates customized reports to give you summaries as well as detailed information about the test coverage. Reports are formatted in an easy-to-read and easy-to-process text format, allowing you to quickly access critical design information.
CoverMeter is efficient and fast, "smart" enough to shut off monitoring when not required. Your testing is efficient, both at run-time and in terms of storage requirements. CoverMeter is so fast that you can use this product as a permanent accessory to all your testing.
CoverMeter is comprehensive when it comes to providing coverage metrics and information. You can be as thorough as you determine necessary in monitoring each element, variable or sub-expression in the design. Its rich and robust set of facilities will enable you to make a deterministic evaluation of the state of design verification for your application. No matter how complex your application may be, CoverMeter can deal with any Verilog design description to gather coverage information without placing undue restrictions on description style or limitations on types of design.
CoverMeter is available for all popular platforms, including Sun SPARC, Hewlett Packard, DEC Alpha and Windows NT platforms. And CoverMeter works with all Verilog simulators that support the PLI interface standard, including simulators from industry leaders Cadence, Viewlogic and Frontline.
We invite you to call Advanced Technology Center (ATC) at (714) 583-9119 to discuss your code coverage needs with an Account Manager.